The present invention relates to high-speed interface circuits in general and more particularly to circuits for filtering transient voltages received at a high-speed interface circuit.
Interface circuits are used to transfer data between two or more integrated circuits. The rate at which this transfer takes place has been increasing dramatically over the last several years. As data rates increase, new problems and difficulties arise. One problem that can come up is the result of transient voltages received at data input pins. Some interface circuitry, for example interface circuitry on field programmable gate arrays manufactured by Altera Corporation of San Jose, Calif., have become so advanced and so fast that they are able to detect these transient voltages and receive them as actual data. Accordingly, a received data stream may become corrupted due to the presence of these transients.
A major cause of these transients is the physical path that signals take when being transferred from one integrated circuit to another. This path typically begins at an integrated circuit output driver and pad. The output driver and pad have a capacitance associated with them. The signal then travels through a bondwire and lead frame of the transmitting integrated circuit, through a PC board trace, and into a receiving integrated circuit. These elements each have inductances and capacitances associated with them. At the receiving integrated circuit, the signal passes through a second lead frame and bond wire to an input gate. This adds even more inductance and capacitance to the path.
When an output driver provides an output such as a clock or data signal, charging currents are generated in these various stray capacitances. The charging currents flow through the inductances creating voltage transients such as ringing, overshoot, and the like.
These output signals typically switch between and first and second logic level. In this case, since the resulting voltage transients are associated with actual data edges, they can be anticipated and compensated for. As an example, set-up and hold times at most of the inputs of Altera's devices can be adjusted to avoid switching transients.
An output driver can also produce a voltage transition when it changes state from either a high or low voltage level to a tri-state or high impedance condition. For example, an output driver may have a resistive load terminated to a voltage midway between a supply voltage and ground. When the output driver changes state from a high logic level near the supply voltage to the tri-state condition, the output transitions from a high level to this midpoint. At this time, voltage transients may result. The same is true when a driver tri-states after providing a low level logic signal near ground, or changes from tri-state to an active high or low logic level.
The transients that occur at these times can be more problematic since they are not associated with an actual data or clock transition. For example, transients on a clock signal may appear as extra clock edges that clock data incorrectly, thus corrupting a received data stream.
It is thus desirable to filter these transient voltages such that they do not cause incorrect data clocking. It is further desirable that this filtering be done in a way that does not degrade circuit performance.